1. Field of the Invention
The present invention relates to a semiconductor memory device, and, in particular, to a divided bit line type dynamic random access memory having plural pairs of main bit lines each of which has sub-bit lines coupled thereto through respective transfer gates.
2. Description of the Related Art
With the increasing demand for high performance and reliability of large digital system, techniques for highly integrated dynamic random access memories (hereinafter referred to as "dRAM's") become indispensable. The divided bit line technique, one of such techniques, is considered promising to provide super large scaled dRAM's. According to this technique, each of parallel bit line pairs formed on a chip substrate is coupled with plural pairs of sub-bit lines. Each sub-bit line has a given number of memory cells coupled thereto and is coupled to the associated main bit line pair through the respective transfer gate. When a memory cell is selected, the transfer gate of the sub-bit line pair including this selected cell is opened and a data voltage from the selected cell is supplied to the associated main bit line pair. A sense amplifier provided to this main bit line pair amplifies the cell data voltage and outputs the amplified data voltage onto output lines.
Such a type of dRAM is, however, facing the problem of making it difficult to reduce dissipation power and increase the data accessing speed. According to the conventional divided bit line type dRAM, charging/ discharging occurs on a main bit line pair having a several times larger capacity than a divided bit line every time data readout from, and data restoring in, a memory cell is executed, thus increasing the dissipation power of the dRAM. In addition, at the time of data reading from or data restoring in the dRAM, the main bit line pair remains coupled to both of the sense amplifier for the main bit lines and the associated divided bit lines until the main bit line pair is completely charged or discharged so that it has the upper limit or lower limit potential of the full potential variation range corresponding to the potential difference between the source voltage Vdd and ground potential Vss. As a result, the capacitive load on this main bit line pair is undesirably increased. This delays the data restoring in the memory cell of a selected divided bit line and/or delays the sensing operation of the main bit line sense amplifier, thus deteriorating the high speed operation of the dRAM.
The following specifically describes the above problem with reference to a 16 megabit dRAM designed using the conventional divided bit line structure. Given that each of 2048 main bit line pairs is coupled with 8 divided bit lines each having 256 memory cells, the capacity of the main bit line pair is 3 to 4 picofarads (pF) and the capacity of each divided bit line is 0.6 to 1 pF. With the one cycle time of the reading operation of the dRAM being 200 nanoseconds, the charging/discharging current flowing through the main bit line and divided bit line at a single refreshing time is 76.8 mA; here, the source voltage Vdd is 5 V and precharge voltage is Vdd/2. In this case, the dissipation current of the divided bit line is 15.36 mA. That is, the dissipation current of the main bit line pair is five times as large as the dissipation current of the divided bit line.